1. Field of the Invention
The present invention relates to an array substrate for a liquid crystal display. More particularly, the present invention relates to an array substrate for a liquid crystal display and a method of fabricating the same.
2. Discussion of the Related Art
With the advent of a more information-oriented society, the field of display devices configured to process and display a large amount of information has rapidly developed. In particular, liquid crystal displays (LCDs) or organic light emitting diodes (OLEDs) have been developed as flat panel displays (FPDs) having excellent performance characteristics, such as a small thickness, light weight, and low power consumption, and has superseded conventional cathode-ray tubes (CRTs).
Among LCDs, an active matrix (AM)-type LCD including an array substrate having a TFT serving as a switching element capable of controlling on/off voltages of each of pixels may have excellent resolution and capability of embodying moving images.
Generally, the LCD is formed by fabricating an array substrate and a color filter substrate and interposing a liquid crystal layer between the array substrate and the color filter substrate.
FIG. 1 is an exploded perspective view illustrating an LCD or an OLED according to the related art.
Referring to FIG. 1, an array substrate 10 and a color filter substrate 20 are attached to each other with a liquid crystal layer 30 therebetween. The array substrate 10 includes a plurality of gate lines 14 and a plurality of data lines 16 to define a plurality of pixel regions P on a first substrate 12. A thin film transistor T is formed at the crossing portion of the gate and data lines 14 and 16 and is connected to a pixel electrode 18 in the pixel region P.
The color filter substrate 20 includes a black matrix 25 corresponding to the gate and data lines 14 and 16 and the thin film transistor T and surrounding the pixel region P, a color filter layer 26 including red (R), green (G) and blue (B) 26a, 26b and 26c arranged in the respective pixel regions P, and a common electrode 28on the black matrix 25 and the color filter layer 26.
Although not shown in the drawings, a sealant is formed between the array substrate 10 and the color filter substrate 20 to prevent leakage of liquid crystal, alignment layers are formed on inner surfaces of the array substrate 10 and the color filter substrate 20, respectively, and polarizers are located on outer surfaces of the array substrate 10 and the color filter substrate 20, respectively.
Moreover, a backlight unit is provided below the array substrate 10. A gate signal is sequentially supplied to the gate lines 14, then the corresponding thin film transistor T is turned on and a data signal is supplied to the data line 16 and then to the pixel electrode 18, and thus an electric field is produced between the pixel electrode 18 and the common electrode 28 to operate liquid crystal molecules of the liquid crystal layer 30, thereby displaying images.
FIG. 2 is a cross-sectional view illustrating an array substrate according to the related art.
Referring to FIG. 2, in the array substrate 10, a gate line (not shown) and a data line 16 cross each other to define a pixel region P, and a gate electrode 55 is formed in a switching region TrA of the pixel region P on a first substrate 11.
A gate insulating layer 58 is formed on the gate electrode 55, and a semiconductor layer 68 including an active layer 62 made of intrinsic amorphous silicon and an ohmic contact layer 66 made of impurity-doped amorphous silicon is formed on the gate insulating layer 58.
Source and drain electrodes 76 and 78 are spaced apart from each other and formed on the ohmic contact layer 66. The gate electrode 55, the gate insulating layer 58, the semiconductor layer 68 and the source and drain electrodes 76 and 78 form a thin film transistor Tr.
A passivation layer 82 is on the source and drain electrodes 76 and 78 and includes a drain contact hole 85 exposing the drain electrode 78. A pixel electrode 18 is formed on the passivation layer 82 in the pixel region P contacts the drain electrode 78 through the drain contact hole 85.
The gate line has a predetermined thickness and width, and the data line 16 has a predetermined thickness and width.
As the size of the LCD increases, the gate line and the data line become longer. This causes an increase of resistance in the signal line, and thus a signal delay occurs. Accordingly, signal deformation and operation defects are caused, and the display quality is degraded.
To prevent such a signal delay, the signal line is required to increase in thickness and/or width. However, in the case of an increase in width, aperture ratio is reduced. In the case of increase in thickness, a step portion becomes great, and this causes disconnection of a component over the signal line. Moreover, the step portion causes vacant space at sides of the signal line, insulation capability is degraded, and thus short-circuit between the signal line and a conductive component to be formed later may occur.